Non-uniform memory access (NUMA) is a pc memory design used in multiprocessing, where the memory entry time is dependent upon the memory location relative to the processor. Beneath NUMA, a processor can entry its personal native memory quicker than non-native memory (memory native to another processor or memory shared between processors). NUMA is beneficial for workloads with excessive memory locality of reference and low lock contention, as a result of a processor could function on a subset of memory principally or solely inside its own cache node, reducing traffic on the memory bus. NUMA architectures logically observe in scaling from symmetric multiprocessing (SMP) architectures. They had been developed commercially in the course of the nineties by Unisys, Convex Pc (later Hewlett-Packard), Honeywell Data Systems Italy (HISI) (later Groupe Bull), Silicon Graphics (later Silicon Graphics International), Sequent Computer Techniques (later IBM), Knowledge Normal (later EMC, now Dell Applied sciences), Digital (later Compaq, then HP, now HPE) and ICL. Strategies developed by these corporations later featured in a wide range of Unix-like working systems, and to an extent in Windows NT.

Symmetrical Multi Processing XPS-100 household of servers, designed by Dan Gielan of Vast Company for Honeywell Info Systems Italy. Trendy CPUs operate significantly faster than the main memory they use. Within the early days of computing and information processing, the CPU generally ran slower than its personal memory. The efficiency traces of processors and memory crossed in the 1960s with the appearance of the primary supercomputers. Since then, CPUs increasingly have discovered themselves "starved for information" and having to stall whereas ready for knowledge to arrive from memory (e.g. for Von-Neumann structure-based computers, Memory Wave Experience see Von Neumann bottleneck). Many supercomputer designs of the 1980s and nineties focused on providing excessive-velocity memory access as opposed to quicker processors, permitting the computer systems to work on massive data sets at speeds different programs couldn't strategy. Limiting the variety of memory accesses offered the key to extracting high efficiency from a modern laptop. For commodity processors, this meant putting in an ever-rising quantity of excessive-speed cache memory and utilizing increasingly sophisticated algorithms to keep away from cache misses.

But the dramatic increase in measurement of the operating techniques and of the applications run on them has typically overwhelmed these cache-processing improvements. Multi-processor techniques with out NUMA make the problem considerably worse. Now a system can starve several processors at the same time, notably as a result of only one processor can entry the pc's memory at a time. NUMA makes an attempt to address this problem by providing separate memory for every processor, avoiding the performance hit when a number of processors try to deal with the same memory. For issues involving spread data (frequent for servers and similar functions), NUMA can enhance the performance over a single shared memory by an element of roughly the variety of processors (or separate memory banks). One other method to addressing this drawback is the multi-channel memory architecture, in which a linear enhance in the variety of Memory Wave Experience channels increases the memory entry concurrency linearly. After all, not all information ends up confined to a single task, which implies that multiple processor might require the same data.

To handle these circumstances, NUMA methods embrace additional hardware or software program to maneuver information between memory banks. This operation slows the processors attached to these banks, so the general speed increase resulting from NUMA closely depends on the character of the operating tasks. AMD carried out NUMA with its Opteron processor (2003), using HyperTransport. Intel announced NUMA compatibility for its x86 and Itanium servers in late 2007 with its Nehalem and Tukwila CPUs. Almost all CPU architectures use a small amount of very fast non-shared memory known as cache to use locality of reference in memory accesses. With NUMA, sustaining cache coherence across shared memory has a significant overhead. Although less complicated to design and construct, non-cache-coherent NUMA systems grow to be prohibitively advanced to program in the standard von Neumann architecture programming mannequin. Sometimes, ccNUMA uses inter-processor communication between cache controllers to keep a consistent Memory Wave picture when a couple of cache shops the identical Memory Wave location.