AUSTIN, Texas, Could 2, 2018 - The DDR PHY Interface (DFI) Group today launched model 5.Zero of the specification for interfaces between excessive-pace memory controllers and bodily (PHY) interfaces to assist the requirements of future cell and server Memory Wave requirements. The DFI specs, broadly adopted throughout the memory trade, allow higher interoperability. The DFI Group included several interface enhancements on this latest specification. The new model of the specification provides protocol help for the most recent DDR and low-power memory applied sciences. Earlier variations of the specification outlined memory coaching across the interface between the memory controller and the PHY. The brand new specification completely transitions to PHY-independent training mode where the PHY trains the memory interface with out involving the controller. Different interface enhancements embody lower power enhancements, providing a PHY-unbiased boot sequence, increasing frequency change assist, and defining new controller-to-PHY interface interactions. "The business is starting to embrace new low-energy and DDR memory technologies, together with high-performance units such as servers, storage, and networking